Eagle Tutorial and Project Design Rules
Follow this tutorial step by step. It first details the creation of parts, the understanding of which allows the designer to learn the rest of the program quite quickly.
Also included are project specific design rules and guidelines.
Installation and Startup
Install the software and start it up.
Allow it to create the projects directory on startup.
Configuration
Important
After installing a new version of Eagle, these configuration settings must be applied again.
Use the following settings:
Vector Font Default
In the schematic and library editor windows, choose “Options/User Interface”. Check the “Always vector font” option.
Also check “Persistent in this drawing”. This saves the setting with the project instead of just locally for the user’s computer. If the project is transferred to another computer or a new Eagle version is installed, the setting will be remembered with the board.
The user manual suggests always using the “vector” font so that the final output will match the screen. Text for labels such as component values and names default to “proportional” and you normally would have to change this all the time. There seems to be no way to specify the font for pin names. Checking the above options forces all of these fonts to use “vector”.
You can also change the “Always vector font” option from the control panel. Clicking on a schematic or board file listed in the left pane and then using Options/User Interface from the main menu allows the option to be changed for the selected file. Highlighting a project folder will change the option for both the schematic and board file. The “Persistent in this drawing” option can only be changed from inside the schematic or board editor.
Note 1:
If you get stop mask / silkscreen spacing errors after transferring a project to another computer or upgrading to a new Eagle version, vector fonts were probably being applied on one computer but not the other. Checking the “Persistent in this drawing” option will solve this.
Note 2:
If you open a schematic or board and turn on these options, you must explicitly save the file to make sure they are stored. If you close the file without saving, no warning will be given and the settings will not be stored.
Turn off Page Listing in Xref Labels
The default format for the “Xref” Labels is to display the page number and row/column of the next occurrence of the net named in the label. This can result in a label which expands unpredictably depending on whether or not the net appears on another page.
Disable this in the schematic editor window by choosing “Options/Set”, choose the “Misc” tab, and change the “Xref label format” entry to “%F%N”.
Creating a New Library and Copying Parts
Expand “Libraries”.
These are the part libraries.
Choose “File/New/Library” – a new “Library” window will open.
Choose “File/Save” in the “Library” window – save it as “Test.lbr”.
You should have two windows open, “Library” (with “Test.lbr”) and “Control Panel”.
Go to the “Control Panel”, make sure “Libraries” is still expanded.
Find “74xx-us.lbr” and expand it.
Right click on “74*00”.
Click on “Copy to Library”.
This copies the part to the “Test” library which you have currently opened in the “Library” window.
NOTE: It won’t show up in the “Test” library in “Control Panel” until you “File/Save” in the “Library” window. Using “Save” in that window saves the entire library. If you close the window without saving the copied part, it will not be saved in the destination library.
Now you can play with the part without destroying the original.
Symbols, Devices, and Packages
Browse down to your new library “Test.lbr” in the “Control Panel” window and expand it.
The program uses with three pieces to form a component:
Symbols, Devices, Packages
You can see the Devices and Packages listed. The Symbols are not listed, but get copied from directory to directory when any Device to which they are connected gets copied.
Every device starts with a Symbol. This is where the part is drawn and pins placed. For a multi-gate part like a NAND gate, you draw one gate. For a part without multiple gates (a DSP for instance), you draw the entire part in one symbol.
| NOTE: For parts without gates that we will be creating (DSPs, CPLDs, A/Ds), do not use the special “Power Pins” which are hidden and automatically connected to the appropriate power net. We need to see the power pins and connect them ourselves for these parts – make them “In” pins. |
After drawing the Symbol, you create a Device and add one or more of the Symbols. You then add Packages to the Device and connect the pins to the pads. The Package is the layout for the circuit board.
Creating, Copying, and Modifying Packages
In your new “Test” package you should have “74*00” (a device), “DIL14” (a package), “LCC20” (a package), and “SO14” (a package). Note that the symbols are not shown in the “Control Panel” window – they are only accessible from within the “Library” window.
In the “Library” window, choose “Library/Package” or click the “Package” symbol on the tool bar.
The “Edit” window will open. The Packages in the Library should be displayed (make sure you are still using your “Test” library). You can switch to view Devices (Dev), Packages (Pac), or Symbols (Sym). Select “DIL14” and then “OK”.
The package will be displayed. Choose “Draw/SMD” – you will receive an error message that the Package is in use. You cannot add or remove pads/SMDs for a Package that is already being used by one or more devices because it will mess up the pin to pad assignments.
| Note: The SMD and PAD shortcuts are displayed in the left toolbar but you may not be able to see them unless you make the Library window bigger. |
To create a package you can play with, see the next section.
Copying a Package
This is NOT intuitive!
The “File/Save As” function in the “Library” window does not save the currently displayed Dev/Sym/Pac under a new name – it saves the entire library under a new name. All of the “File” options are related to the Library itself.
Note that the “Variant” option creates variants which all use the same package. The only thing you seem to be able to change is pin assignments – if you edit the package of a variant, the package for all variants is edited. So this doesn’t really create a copy of a package which you can modify without affecting all the other variants.
To create a true copy of a package:
Method 1 (read from the Internet, a bit messy)
Open the library containing the package to be copied.
Choose “Library/Package”, select the package to be copied. (ex. SO14)
Choose “View/Display Hide Layers”. Click “All”, then “OK” to display all layers.
Choose “Edit/Group”
Click and hold the left mouse button in the upper left corner of the display, drag to include everything in the window. Release button – the selected components become brighter.
Select “Edit/Cut”. This really means “Copy” as it does not “Cut”. Click somewhere on the selected area.
Choose “Library/Package”. In the “New” field, type the name for your new package, click “OK”, then “Yes”.
Choose “Edit/Paste” and position the pasted info and left click.
| NOTE: I read on the Internet that you need to make sure the grid settings (especially inches/mm) are the same from the old package to the new package – not sure if this is still true. |
Method 2 (from experimentation)
The main problem is that Eagle won’t copy a package into the same library. Use a scratch library to copy the package temporarily, rename it, then copy it back.
Create a new library called “Scratch” (or whatever).
Open the “Scratch” library.
Find the package in the “Control Panel” in the original library, right click on it and choose “Copy to library” and the part will be copied to the open “Scratch” library.
In the “Library” window, choose “Library/Rename” and give the package a new name. Close the “Scratch” library, saving it.
Open the library which held the part to be copied and in which you want the new copy. Browse to the “Scratch” library in the “Control Panel” and right click on the part you just renamed, choose “Copy to library” and the package will be copied to the open library with it’s new name. You will now have the original package with it’s original name and a copy with the new name. Close the library, saving it.
Of course you can copy a part from library to library, renaming it as necessary. The use of the scratch library is only needed if you are trying to copy a part in the same library.
Creating a Package
Open a library.
In the “Library” window, choose “Library/Package”.
In the “New” field, type the name of the new package and click “OK”.
– OR –
Copy an existing package to a new name as described above.
Modifying a Package
Make a new copy of the “SO14” package which should be in your new “Test” library after you copied the “74*00” device to it. Use Method 2 described above, calling the copy “SO14-COPY”.
Open the “Test” library, open the “SO14-COPY” package using “Library/Package”.
Increase the size of the “Library” window so that you can see the “Pad”, “Hole”, and “SMD” shortcuts at the bottom of the toolbar at the left if they are not already visible.
Click on the “SMD” shortcut and place a “SMD” pad. You will not get an error this time because this copy of the package is not yet attached to any device.
Click on the “Layers” shortcut, click “NONE” to hide all layers, then click on the number “1” by the first layer, then “OK” to view it. Look at each layer alone one by one to see what is typically placed on each layer for a component.
|
Layers Used by a typical surface mount package: Top – pads The tStop & tCream layers are automatically created when you place a pad unless you turn off “Stop” or “Cream” for any pad in the “Info” window. The size of these objects is related to the size of the pads, controlled by the Design Rules. To access these settings, in the “Control Panel” window, scroll down past the libraries to “Design Rules”, double click on it, choose the “Masks” tab. |
| Project Specific Design Rules |
| For the Capulin project, all SMD pads need to be modified to add an extra millimeter of pad visible beyond the pin to ease hand assembly. Unfortunately, the origin of the pad is in the center, so increasing the size adds length to both ends. The millimeter has to be added and then each pad must be shifted outward.
A new library name “Capulin” should be created and all parts used copied to that library and then modified if necessary. As a matter of course, for all boards a new library should be created using the name of the board. All parts used should be copied there regardless of whether or not they are modified. Thus when a project is transferred between designers, the library should go with the board to make things simpler. |
You can look at the settings for any object by first clicking on the “i” shortcut and then clicking on the object.
When you place a pad, it is given a default name such as “P$1”. Per the Eagle help, rename this with a name such as “1”, “RESET”, “CLK”, etc. – you must do this for each pad.
The default settings for each SMD can be changed by using the “Change” shortcut (looks like a wrench). For example, you can turn “Thermals” on or off – all subsequent SMDs will use the selection.
If you create a new library for each board and copy the parts to it, you can modify those parts as necessary – it is not necessary to copy the parts within the library (which is difficult as described above) unless you actually need two versions of the part on the board.
You can modify such things as pad size and location in a package even if the package is already attached to a device. You cannot add or remove pads. Most of the modifications we will need to meet the project guidelines are to the size and position of pads and holes.
Make sure text settings are consistent for parts used on any board.
Working with Symbols
Each Device uses Symbols – Symbols define the outline, pins, etc. The Device ties one or more copies of a Symbol together with one or more Packages. The same IC may have different packages – through hole, SMD, etc.
Open the “Test” library, choose “Library/Symbol”, select 7400. This should have been copied over when you copied the “74*00” device to your new library.
Click on the “Layers” shortcut and turn on the “Pins” layer. This will show the pins and text such as “In 1”, and “Out 0”. These are NOT the pin names – these represent the pin’s I/O direction and swap level. To see the pin names, click the “Info” button and then click on each pin. The inputs are named “I1”, “I2”, and “O”. Since there is only one output, it does not need a number.
The swap level tells which pins can be swapped by the Auto-Router if it makes the layout simpler. A swap level of “0” means the pin cannot be swapped. The two inputs on the gate are interchangeable, thus their swap levels are both set to “1” – any pins with the same swap level can be swapped. There is only one output pin so it’s swap level is “0” – it cannot be swapped.
Later when the Device is created, each gate also has a swap level so an entire gate can be swapped. The Auto-Router can even swap to a gate in a different, identical component.
On the Info for a pin, setting visible to “Pin” or “Both” displays the pin name on the “Names” layer and displays it in the schematic – not used for gate devices where the symbol explains the use of the pin, but used for complex devices like a DSP where each pin needs a textual explanation. For “Pad” or “Both”, the pad number is also displayed. You will not see the pin numbers when editing the Symbol and you will not see them when you add the Symbol to a Device UNTIL you connect the pins to pads of a package. The pad numbers are retrieved from the package.
Since Symbols don’t show up in the “Control Panel” window, the only apparent way to copy them is to use the “All layers on, group, cut, create new symbol, paste” method.
When you open a symbol, the Pin layer is usually turned off. Turn it on to work with the pins.
You will notice that there are no power pins defined for the gate. For a multiple gate device, the power pins are created as a separate symbol. The device then includes the power pins symbol along with the gate symbols to tie them all to the package.
Open the symbol “PWRN”, turn on the “Pins” layer, and use the “Info” shortcut to view the settings for each pin. The direction for each pin is set to “Pwr” and they are named “VCC” and “GND”. When such a device is placed on the schematic, the power pins will not be displayed but are automatically connected to the nets “VCC” and “GND”.
If multiple ground or power pins exist, they will all have to have the same name – “GND” for example. To handle this, name them “GND@1”, “GND@2”, and so on. Eagle understands these pins have the same name and will connect them to the “GND” net and ignore the “@1” suffix.
Use an exclamation point as a prefix (“!RESET”) to create a bar over the pin name to show that it is active low.
|
Direction Options for Pins |
|
| NC | not connected |
| In | input |
| Out | output (totem-pole) |
| I/O | input/output (bidirectional) |
| OC | open collector or open drain |
| Hiz | high impedance output (3 state) |
| Pas | passive (resistors, capacitors, etc.) |
| Pwr | power input (Vcc, Gnd, Vss, Vdd, etc.) |
| Sup | general supply (not for components – use for Gnd symbol, etc. |
“Sup” is not used for devices (components). It is used for “GND”, “VCC” symbols, etc. To have hidden power pins automatically connected, objects with “Sup” pins with the same name as the power pins must be placed. If a “GND” symbol is placed (which has a GND Sup pin) then all “GND” power pins on components will be connected together. Thus, the power pin to a board should be connected to a “GND” symbol – this is the supply for the “GND” net.
To see an example of the use of the “Sup” option, look at the symbols in the libraries: supply1.lbr, supply2.lbr, supply-dummy.lbr
| Project Specific Design Rules |
| For all parts not having multiple gates (DSPs, CPLDS, A/Ds), do NOT set the power pins to “Pwr”. Set them as “In” so they will be displayed and must be explicitly connected to the appropriate net by the designer. |
Working with Devices
As with packages and symbols, you can create and copy devices as previously described.
Open the “Test” package, choose “Library/Device”. Create a new device named “DEV1” by typing the name into the “Name” field and clicking “OK”.
Click the “Add” shortcut (or use “Edit/Add”), select “7400”, click “OK”. Position the gate in the upper left corner. Add another gate (symbol).
To move the symbols around, click on the “Move” shortcut (or “Edit/Move”), then click on the symbols to select and move them. If you have trouble selecting a symbol, look for the “+” near the middle of the symbol and click on that.
Use the “Info” shortcut to change the gate names to “A”, “B”, etc. The pin names will be referred to as “A.I1”, “B.I1”, “A.O” – combining the gate name with the pin names already defined in the gate symbol.
Use the “Info” shortcut to set the “Swap Level” for each gate – any gate can be swapped with another having the same Swap Level by the Auto Router to simplify routing. A Swap Level of “0” means a gate cannot be swapped.
Use the “Info” shortcut to set the “Add Level”, usually to the value “Next”. Symbols set to “Next” are added one after the other when a gate is added to the schematic – the first add places gate “A”, the second gate “B”, etc.
The “Must” value of “Add Level” forces the symbol to be added to the schematic whenever any other symbol is added. This is handy if there is something that must be displayed any time a gate for the device is added.
Power pin symbols should have an “Add Level” of “Request”. This allows the pins to be added to the schematic if the designer requests such, but the symbol does not add to the gate count, i.e. a device with a single logic gate does not look like a device with two symbols (the logic gate and the power pins) because “Request” symbols are not counted as gates.
| Values for Add Level | ||
| Next | If a device has more than one gate, the symbols are fetched into the schematic with Addlevel Next. | |
| Must | If any symbol from a device is fetched into the schematic, then a symbol defined with Addlevel Must must also appear. This happens automatically. It cannot be deleted until all the other symbols in the device have been deleted. If the only symbols remaining from a device are Must-symbols, the DELETE command will delete the entire device. | |
| Always | Like Must, although a symbol with Addlevel Always can be deleted and brought back into the schematic with INVOKE. | |
| Can | If a device contains Next-gates, then Can-gates are only fetched if explicitly called with INVOKE. A symbol with Addlevel Can is only then fetched into the schematic with ADD if the device only contains Can-gates and Request-gates. | |
| Request | This property is usefully applied to devices’ power-symbols. Request-gates can only be explicitly fetched into the schematic (INVOKE) and are not internally counted. The effect of this is that in devices with only one gate and one voltage supply symbol, the gate name is not added to the component name. In the case of a 7400 with four gates (plus power supply) the individual gates in the schematic are called, for example, IC1A, IC1B, IC1C and IC1D. A 68000 with only one Gate, the processor symbol, might on the other hand be called IC1, since its separate voltage supply symbol is not counted as a gate. | |
Use the “Prefix” button near the lower right of the “Library” window to set the prefix to be used on the schematic for the device (U, T, X – as in U1, U2, T3).
Use the “Value” button near the lower right of the “Library” window to specify whether a value should be associated and displayed with the device. Resistors, capacitors and such usually have values.
Connecting With the Package(s)
After adding all the symbols (gates, power pin symbols, etc.), Packages are selected. This is done by using the “New” button at the lower right corner of the “Library” window. This doesn’t actually create a new package – it allows you to select one or more existing packages to be associated with the device.
After selecting the packages, they will be displayed in the window to the right. Click on a package and then click the “Connect” button. The device pins and package pins will be displayed in a window. Click on the device pin in the left box and then the package pin in the center box and then click “Connect”. The pins will be moved to the box on the right. Connect all pins or the package will be displayed with an exclamation point. Repeat for all packages.
Title Blocks
Add a FRAME_B_L to each page, add company name, document number, and functional description. These text items are not part of the frame, so to copy everything a group copy must be performed.
You can add the frame to an otherwise blank page and then copy it as a group to the other pages, then delete the blank page when the schematic is done. This simplifies copying the frame as a group without also copying any schematics inside the frame.
Placement Details
Add FRAME_B_L from the frames.lbr library which is installed with the Eagle program.
Position the frame at 0,0
Give frame value of FRAME_B_L (or similar) to avoid ERC error.
The Nets layer is used to give the text a more visible green color.
Company Name:
Position: 13.0, 1.0
Size .254
Ratio 8%
Font: Proportional
Layer: 91 Nets
Document number:
Position: 14.4, 0.4
Size .15
Ratio 8%
Font: Proportional
Layer: 91 Nets
Functional Description:
Position: 13.0, 0.25
Size .08
Ratio 8%
Font: Proportional
Layer: 91 Nets
(reduce size if text too long to fit)
Board Layer Usage
1:
The fiduciary markers (fiducials) are on layer 49, Reference. Nothing else should be on this layer as it is included on the CAM output with every other layer so that they can be aligned. Only three markers should be used and should be the same shape, size, and line thickness as on this board. Keep the markers close to the outline of the board so that when you “Zoom All” they will not force the magnification to be small.
2:
The final shape to which the board is to be cut is located on layer 48, Document. Make the board outline 0.005″ in width. All measurement data should be on this layer. This outline will be very similar to the outline on layer 20, Dimension.
3:
Eagle uses layer 20, Dimension to hold the outline it uses to constrict routing. In general, this outline should closely match the outline on Layer 48, Document. The difference is that the layer 20 outline may not have certain notches or holes which might violate the Design Rules by being too close to a component or trace but nonetheless must be included when the board is cut from the panel. If extra board space and copper must be included in the design up until the final cut, this is done on the layer 20 outline. Since the board will be cut to match the layer 48 outline, the extra space and copper will be removed on the final cut. This is useful for adding an electrode connection bar to an edge connector so it can be gold plated – the layer 20 outline will have the extra board space and the copper bar connecting the fingers of the connector while the layer 48 outline will cut the electrode bar off.
4:
All plane layers should have an 80 mil edge free of copper so that the ground plane copper is not exposed or shorted at the edges of the board. This is done by placing a 160 mil (because the line is centered, only half will actually be on the board) line on layer 100 PlaneGlobals (this layer must be created) which traces the outline of the board. Be sure to outline any holes which are to be cut in the board as well. Mounting holes placed using the “Hole” command in Eagle do not need to be outlined as this is done automatically.
5:
Each layer should have its name displayed by writing in text on that layer. Note that on copper layers, this will result in the name being represented by copper (or a lack of copper on the plane layers) so care must be taken not to short to a trace. The solder layer name will default to mirrored writing while all the other layers will have non-mirrored writing. This is fine as it is difficult to know which way each layer will be facing in the stack up. The fiduciary marks will allow the manufacturer to ensure proper registration.
Use the following names:
component layer: “CMP”
inner route 2 : “IN2 (these may be named GND, +5V or similar in the Eagle program – use in2, in3,… regardless)
inner route 3 : “IN3”
…
solder layer: “SOL”
At the present time, only the electrical layers as described above must be labeled.
Cam Processor Job — Creating the Gerber Output
Each job should have it’s own CAM processor job with “.cam” appended to the board name. I have included a CAM job with this example. Please look it over and notice how each section tab specifies the appropriate layers to be included on each plot. This allows the fiducial marks to be included on all layers, the copper free outline to be included on the plane layers, etc.
Requesting a Quote
Here is a sample email template for asking for quotations:
Subject: Quote Request – CUB Control Board Ver 1-0
Please quote the board attached as Gerber plots.
Quantities and Lead Times
————————-
I need at least 2 boards, please quote maximum product for minimum price
Please quote 1 week and 2 week lead times.
Specifications
————–
Board size : 10.85″ x 5.0″ x 0.062″
Material: .062″ FR-4 11 (starts with 1 ounce copper on both sides)
Copper after plating: 2 ounce finish
Copper clad on both sides
Solder mask over bare copper
Silkscreen: Hysol Yellow (component side)
Soldermask: Coates LPI green (both sides)
Layers: 4 electrical + solder mask top, solder mask bottom, silkscreen top
All holes with pad size equal to diameter are non-plated through holes.
Layer Stack Up
—————
component side (*.cmp)
prepeg
Inner 2 (power plane)(*.in2)
core
Inner 3 (power plane)(*.in3)
prepeg
solder side (*.sol)
File List
———
Attached files are as follows:
Gerber report (*.gpi)
Excellon Drill File (*.drd – drill file; *.dri – drill report)
Board Outline and Dimensions (*.dim)
Top Signal (*.cmp)
Inner 2 Signal (power plane) (*.in2)
Inner 3 Signal (power plane) (*.in3)
Bottom Signal (*.sol)
Top Silkscreen (*.plc)
Top Solder Mask (*.stc)
Bottom Solder Mask (*.sts)